1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor wafer, and in particular to an efficient method of manufacturing a semiconductor wafer in a proper chamfered shape.
2. Description of the Prior Art
Conventionally, the following steps performed manufacturing of semiconductor wafers.
(1) Slicing a semiconductor ingot into plural sliced wafers. PA1 (2) Chamfering the outer peripheries of the sliced wafers. PA1 (3) Flattening the chamfered wafers by a process such as lapping. PA1 (4) Removing distortion layer in processing of the chamfered wafers, which is induced during the flattening process, by alkali etching or acid etching. PA1 (5) Polishing at least one side surface of the each etched wafer to obtain mirror-surface wafers.
In the process of flattening, lapping performed by batch processing is preferred due to its high productivity. However, it is quite difficult to obtain desired flatness by the above lapping process if the device processes require high degree of flatness.
Furthermore, following the increasing in diameter of semiconductor wafers, it is quite difficult to lap a semiconductor wafer with diameter greater than 12 inches so as to obtain such high degree of flatness. Additionally, the enlargement of lapping equipment is also a problem.
Therefore, in the process of manufacturing large-diameter semiconductor wafers, instead of batch processing, various types of surface grinding processes are used because the flatness of the semiconductor wafers is much more important than productivity. For example, a double side simultaneous grinding process is brought into public notice. The double side simultaneous grinding process produces high-flatness semiconductor wafers with productivity higher than that of a single-sided surface grinding process. The double side simultaneous grinding process is performed by simultaneously grinding both of the front surface and the back side surface of a semiconductor wafer with an upper grinder and a lower grinder.
Unexamined Japanese Patent Publication No. H9-260314 entitled "METHOD OF MANUFACTURING SEMICONDUCTOR WAFERS" discloses the above various types of surface grinding processes. In H9-260314, processes for flattening the chamfered and sliced wafers by the above-mentioned various types of surface grinding processes such as double side simultaneous grinding process are described.
However, the processes disclosed in H9-260314, the single-sided surface grinding process or the double side simultaneous grinding process have respectively the following disadvantages.
(1) Single-Sided Surface Grinding
FIGS. 8a-8c are side cross-sectional views showing the contours of a semiconductor wafer flattened by a conventional single-sided surface grinding process. FIG. 8a shows a sliced wafer 5a cut off from a semiconductor ingot, and unevenness 52a such as waviness or warp exists on its surface.
To remove the unevenness 52a, the back side surface 51a has to be fixed firmly by a vacuum chuck and then the outer peripheral portion of the wafer 5a is chamfered. As shown in FIG. 8b, because the back side surface 51b is parallel with the adsorption face 50 of the vacuum chuck, the sliced wafer 5a is affixed along the adsorption face 50. As a result, the adsorption face 50 is taken as the working reference plane of the chamfering process.
The wafer 5b chamfered by taking the adsorption face 50 as the working reference plane is guided to be surface-ground in the state of being affixed by the sucker of a grinding machine. The discrepancy between the thickness central plane which is taken as the working reference plane of the surface grinding and the chamfering central plane which is taken as the working reference plane of chamfering will arise according to the inclination of the sliced wafer 5b being sucked. Under this circumstance, a part of the chamfered portion of the wafer 5c will be removed after performing the surface grinding both sides of the wafer 5b (see FIG. 8c).
(2) Double Side Simultaneous Grinding
FIGS. 9a-9c are side cross-sectional views showing the contours of a semiconductor wafer flattened by a conventional double side simultaneous grinding process. As shown in FIG. 9a, chamfering process is performed before double side simultaneous grinding process. The back side surface 61a of the sliced wafer 6a is taken as the working reference plane during chamfering process in the same way as the above-mentioned single-sided surface grinding process.
However, in the process of double side simultaneous grinding process, both sides of the sliced wafer 6a are simultaneously ground. Therefore, the contact surfaces 60a and 60b at which the grindstones contact with the unevenness surfaces are taken to be the working reference plane of grinding. In the case that the unevenness of the sliced wafer 6a is significant, the discrepancy will occur between the working reference plane of grinding and the working reference plane 60c of chamfering (see FIG. 9b). Consequently, a part of chamfered portion will be removed (see FIG. 9c).
Breakage and chipping are inclined to take place in the wafers with their chamfered portions partly removed during the succeeding processes. Even if breakage or chipping did not happen, there still exists a danger of being unable to meet the standard for chamfered shape, which is required by device proceedings.